1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to apparatus and methods for reducing the variation in output current of a bit line sense amplifier structure.
2. Related Art
A dynamic random access memory (DRAM) uses a sense amplifier to detect and amplify data stored in a memory cell. The sense amplifier is connected to bit lines of the memory cell, and compares the voltage level of a charge shared bit line with the pre-charge voltage of the bit line to discern memory cell data. A sense amplifier may be connected to one memory block to sense memory cells in the memory block, or it may be connected to two memory blocks to selectively sense memory cells in each of the two memory blocks.
As shown in FIG. 1, a general bit line sense amplifier includes, as a main component, a sense amplifying unit 10a having two pairs of CMOS inverters I1 and I2 connected to each other in a latch structure.
In such a bit line sense amplifier, when a word line (not shown) is activated, signals are transmitted from a memory cell (not shown) to the sense amplifying unit 10a through a pair of bit lines BLT and BLB. The levels of an RTO signal line and an SB signal line that are maintained at a predetermined voltage (for example, Vcore/2) selectively increase and decrease, which makes it possible for the sense amplifying unit 10a to perform a sensing operation. Accordingly, the bit line BLT changes to a level Vcore (or a level Vss), and the bit line bar BLB changes to the level Vss (or the level Vcore). The RTO signal line and the SB signal line are connected to a bit line sense amplifier driving circuit that is provided in the bit line sense amplifier.
FIG. 2 is a plan view illustrating the sense amplifying unit 10a of FIG. 1 integrated on a substrate.
Referring to FIG. 2, a PMOS active region 20 and an NMOS active region 30 are provided on a semiconductor substrate (not shown). Gate electrodes g1 and g2, and gate electrodes g3 and g4 are provided in the PMOS active region 20 and the NMOS active region 30, respectively, and source and drain regions (not shown) are formed in the active regions 20 and 30 at both sides of each of the gate electrodes g1, g2, g3, and g4.
A first line M1 is formed such that the gate electrode g1 of the first PMOS transistor P1 forming the first inverter I1 is connected to the drain of the second NMOS transistor N2 forming the second inverter I2, and a second line M2 is formed such that the gate electrode g2 of the second PMOS transistor P2 forming the second inverter I2 is connected to the drain of the first NMOS transistor N1 forming the first inverter I1. In addition, a third line M3 is formed such that the gate electrode g3 of the first NMOS transistor N1 is connected to the drain of the second PMOS transistor P2, and a fourth line M4 is formed such that the gate electrode g4 of the second NMOS transistor N2 is connected to the drain of the first PMOS transistor P1.
The first and second PMOS transistors P1 and P2 are symmetrical with respect to a vertical axis such that they share one source region, and an RTO line M6 is connected to the common source of the first and second PMOS transistors P1 and P2. Meanwhile, unlike the PMOS transistors, the sources of the first and second NMOS transistors N1 and N2 are independently formed, and SB lines M7 are connected to the sources of the first and second NMOS transistors N1 and N2, respectively. In FIG. 2, a character ‘C’ indicates contact portions between the regions of the transistors and the lines.
When the sense amplifying unit is arranged and formed on the semiconductor substrate, a mask for manufacturing the transistors may be misaligned, which may cause the gates g1, g2, g3, and g4 to be shifted, or the contact portions C to be shifted in a predetermined direction. When one or more of the gates g1, g2, g3, and g4 are shifted, and/or one or more of the contact portions C are shifted in a predetermined direction, output currents from the transistors may be different from each other.
It is known that a MOS transistor has different drain currents Ids in a linear region and a saturation-region. The drain currents Ids in each region are defined as follows:IdSLinear={(Vgs−Vt)·Vds−Vds2/2}, and   (1)IdSaturation=(Vgs−Vt)2,
where Vgs indicates a gate-source voltage, Vt indicates a threshold voltage, and Vds indicates a drain-source voltage.
In equation (1), the different drain currents in the linear region and the saturation-region are defined as a function of Vgs. As described above, when the position of the gate electrode is changed, the gate-source voltage Vgs is also changed, which causes the output currents of the MOS transistors to differ from each other.
For example, when the gate electrodes g1 and g2 of the first and second PMOS transistors P1 and P2 are shifted toward the left side of the drawing by a predetermined distance due to a manufacturing error (or variable), the distance between the gate electrode and the source region of the first PMOS transistor P1 increases, and the drain current is reduced. On the other hand, the distance between the gate electrode and the source region of the second PMOS transistor P2 decreases, and the drain current increases. Therefore, different currents (drain currents) are output from the PMOS transistors, which is not preferable.
Similarly, when the gate electrodes g3 and g4 of the first and second NMOS transistors N1 and N2 are shifted toward the left side (or the right side) of the drawing due to a manufacturing error, the distance between the gate electrode and the source region of the first NMOS transistor N1 decreases, and the drain current increases. On the other hand, the distance between the gate electrode and the source region of the second NMOS transistor N2 increases, and the drain current increases. Therefore, different currents (drain currents) are output from the NMOS transistors, which is not preferable.
As described above, when the gate electrodes g3 and g4 of the first and second NMOS transistors N1 and N2 are shifted toward the left side of the drawing, the positions of the drains of the first and second PMOS transistors P1 and P2 respectively connected to the gate electrodes g3 and g4 are changed. Therefore, in the first PMOS transistor P1, the distance between the gate electrode and the drain increases, and in the second PMOS transistor P2, the distance between the gate electrode and the drain decreases. As a result, an error in the drain current occurs in the PMOS transistors.
Such mismatches and/or errors formed in the transistors forming the sense amplifying unit can cause a resulting sense amplification error as illustrated by the circled areas of the graph illustrated in FIG. 3. That is, when the charge shared bit line BLT should be sensed at a low level of “0”, the charge shared bit line BLT may be sensed at a high level of “1” due to errors in the output currents of the transistors. Similarly, when the charge shared bit line BLT should be sensed at a high level of “1”, the charge shared bit line BLT may be sensed at a low level of “0” due to errors in the output currents of the transistors.